ShashankVM's Stars
opencv/opencv
Open Source Computer Vision Library
isocpp/CppCoreGuidelines
The C++ Core Guidelines are a set of tried-and-true guidelines, rules, and best practices about coding in C++
gnuradio/gnuradio
GNU Radio – the Free and Open Software Radio Ecosystem
YosysHQ/yosys
Yosys Open SYnthesis Suite
YosysHQ/picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
google/skywater-pdk
Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
lowRISC/opentitan
OpenTitan: Open source silicon root of trust
quic/aimet
AIMET is a library that provides advanced quantization and compression techniques for trained neural network models.
nvdla/hw
RTL, Cmodel, and testbench for NVDLA
corundum/corundum
Open source FPGA-based NIC and platform for in-network compute
RRZE-HPC/likwid
Performance monitoring and benchmarking suite
cycfi/q
C++ Library for Audio Digital Signal Processing
MatthieuCourbariaux/BinaryNet
Training Deep Neural Networks with Weights and Activations Constrained to +1 or -1
chipsalliance/riscv-dv
Random instruction generator for RISC-V processor verification
chipsalliance/Cores-VeeR-EH1
VeeR EH1 core
black-parrot/black-parrot
A Linux-capable RISC-V multicore for and by the world
zachjs/sv2v
SystemVerilog to Verilog conversion
accellera-official/systemc
SystemC Reference Implementation
pulp-platform/pulp
This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
quic/aimet-model-zoo
intel/systemc-compiler
This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
tukl-msd/DRAMSys
DRAMSys a SystemC TLM-2.0 based DRAM simulator.
cpc/openasip
Open Application-Specific Instruction Set processor tools (OpenASIP)
Minres/SystemC-Components
A SystemC productivity library: https://minres.github.io/SystemC-Components/
accellera-official/PySysC
Public repository for PySysC, (From SC Common Practices Subgroup)
Arteris-IP/tlm2-interfaces
contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols
Minres/DBT-RISE-RISCV
An instruction set simulator based on DBT-RISE implementing the RISC-V ISA
Minres/SystemC-Quickstart
A simple C++ CMake project to jump-start development of SystemC models and systems
amiq-consulting/amiq_rm
MISTLab/trap-gen
Automatically exported from code.google.com/p/trap-gen