bendl

bendl's Stars

• microsoft/Web-Dev-For-Beginners

  24 Lessons, 12 Weeks, Get Started as a Web Developer

  Language:JavaScript83.8k2.7k29212.4k

• changkun/modern-cpp-tutorial

  📚 Modern C++ Tutorial: C++11/14/17/20 On the Fly | https://changkun.de/modern-cpp/

  Language:C++24.3k6221333k

• tpope/vim-surround

  surround.vim: Delete/change/add parentheses/quotes/XML-tags/much more with ease

  Language:Vim Script13.5k130323445

• google/or-tools

  Google's Operations Research tools:

  Language:C++11.4k3083k2.2k

• madd86/awesome-system-design

  A curated list of awesome System Design (A.K.A. Distributed Systems) resources.

  9.8k19861.1k

• qvacua/vimr

  VimR — Neovim GUI for macOS in Swift

  Language:Swift6.7k117934220

• npryce/adr-tools

  Command-line tools for working with Architecture Decision Records

  Language:Shell4.7k8963589

• BrunoLevy/learn-fpga

  Learning FPGA, yosys, nextpnr, and RISC-V

  Language:C++2.6k8574249

• pConst/basic_verilog

  Must-have verilog systemverilog modules

  Language:Verilog1.7k601384

• The-OpenROAD-Project/OpenLane

  OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

  Language:Python1.4k61963379

• XUANTIE-RV/openc910

  OpenXuantie - OpenC910 Core

  Language:Verilog1.2k4528314

• SymbioticEDA/riscv-formal

  RISC-V Formal Verification Framework

  Language:Verilog589394199

• gaih/introduction-to-machine-learning-archived

  Language:Jupyter Notebook565301518

• ben-marshall/awesome-open-hardware-verification

  A List of Free and Open Source Hardware Verification Tools and Frameworks

  49943548

• raysalemi/uvmprimer

  Contains the code examples from The UVM Primer Book sorted by chapters.

  Language:SystemVerilog499560205

• MoonbaseOtago/vroom

  VRoom! RISC-V CPU

  Language:Verilog48227822

• ultraembedded/core_ddr3_controller

  A DDR3 memory controller in Verilog for various FPGAs

  Language:Verilog37919590

• RTimothyEdwards/open_pdks

  PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open processes.

  Language:Python2972022087

• YosysHQ/fpga-toolchain

  Multi-platform nightly builds of open source FPGA tools

  Language:C292125526

• dpretet/async_fifo

  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

  Language:Verilog28611677

• jamesbowman/swapforth

  Swapforth is a cross-platform ANS Forth

  Language:Forth281366156

• timvideos/litex-buildenv

  An environment for building LiteX based FPGA designs. Makes it easy to get everything you need!

  Language:Python2152414479

• ucsdsysnet/corundum

  Open source FPGA-based NIC and platform for in-network compute

  Language:Verilog18616045

• AUCOHL/Fault

  A complete open-source design-for-testing (DFT) Solution

  Language:Swift143114430

• efabless/caravel_mpw-one

  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

  Language:Verilog1351737136

• cliffordwolf/PonyLink

  A single-wire bi-directional chip-to-chip interface for FPGAs

  Language:Verilog11614015

• stevehoover/RISC-V_MYTH_Workshop

  Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop

  Language:TL-Verilog789132

• AntonovAlexander/activecore

  Hardware generation library based on "Kernel IP" (KIP) cores: programmable execution kernels inferred from microarchitectural templates

  Language:Assembly281023

• bendl/verilog_cpu_and_compiler

  Verilog in-order RISC CPU with high-level software compiler

  Language:C23160

• MichaelLegg/AdventOfCode2021

  AdventOfCode2021

  Language:TypeScript1500