j-marjanovic's Stars
atom-computing/lombardo-extender-board
Extender board for the front-panel connector on the DAMC-FMC2ZUP carrier
MicroTCA-Tech-Lab/pymmcmb
Python binding for mmc-mailbox
srush/Tensor-Puzzles
Solve puzzles. Improve your pytorch.
sifive/meta-sifive
SiFive OpenEmbedded / Yocto BSP Layer
mciepluc/cocotb-coverage
Functional Coverage and Constrained Randomization Extensions for Cocotb
eugene-tarassov/vivado-risc-v
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
fyquah/hardcaml_zprize
Hardcaml_zprize implements high performance, open source cryptographic solutions for large scale number theoretic transforms (NTT) and multi-scalar multiplications (MSM) in Hardcaml. Originally developed as submissions to the 2022 ZPrize competition.
fpgasystems/Coyote
Framework providing operating system abstractions and a range of shared networking (RDMA, TCP/IP) and memory services to common modern heterogeneous platforms.
tequilahub/tequila
A High-Level Abstraction Framework for Quantum Algorithms
kontron/python-ipmi
A pure python IPMI library
oscarhiggott/PyMatching
PyMatching: A Python/C++ library for decoding quantum error correcting codes with minimum-weight perfect matching.
EmilioPeJu/MMCTester
Test utility for MMC development
MicroTCA-Tech-Lab/meta-techlab-utils
This is a automatic mirror of the meta-techlab-utils release branch
cocotb/cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
NaturalDocs/NaturalDocs
Natural Docs source code documentation system
pyuvm/pyuvm
The UVM written in Python
MicroTCA-Tech-Lab/mmc-mailbox
Data interface between DMMC-STAMP and AMC payload
SystemRDL/PeakRDL-regblock
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
SystemRDL/PeakRDL
Control and status register code generator toolchain
gsmecher/pyxsi
Python/C/RTL cosimulation with Xilinx's xsim simulator
KastnerRG/pp4fpgas
Parallel Programming for FPGAs -- An open-source high-level synthesis book
ikwzm/fru-print
Print FRU data of CC/SOM EEPROM
UCATLAS/meta-l1calo
OpenEmbedded Layer for L1Calo Projects
newhouseb/onebitbt
Bluetooth PHY based on one-bit input and output
UVVM/UVVM
UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/
MoonbaseOtago/vroom
VRoom! RISC-V CPU
ausbin/nsdo
run a command in a Linux network namespace
MicroTCA-Tech-Lab/libudmaio
Userspace I/O library for Xilinx AXI S2MM DMA
wirebond/nyanritsu_322u17954
The pondering of Nyanritsu 322U17954 RF Base(board)
Xilinx/chipscopy
ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communication Framework) ChipScope Server (cs_server).