kevinku0101

kevinku0101's Stars

• microsoft/qlib

  Qlib is an AI-oriented quantitative investment platform that aims to realize the potential, empower research, and create value using AI technologies in quantitative investment, from exploring ideas to implementing productions. Qlib supports diverse machine learning modeling paradigms. including supervised learning, market dynamics modeling, and RL.

  Language:Python14.7k2888962.5k

• fangzesheng/free-api

  收集免费的接口服务,做一个api的搬运工

  14.6k318491.6k

• Python-World/python-mini-projects

  A collection of simple python mini projects to enhance your python skills

  Language:Python14.5k2811844.7k

• waditu/tushare

  TuShare is a utility for crawling historical data of China stocks

  Language:Python12.7k9821.6k4.3k

• iamshuaidi/CS-Book

  计算机类常用电子书整理，并且附带下载链接，包括Java，Python，Linux，Go，C，C++，数据结构与算法，人工智能，计算机基础，面试，设计模式，数据库，前端等书籍

  11.2k297242.7k

• tuteng/Best-websites-a-programmer-should-visit-zh

  程序员应该访问的最佳网站中文版

  11.2k246111.4k

• twopirllc/pandas-ta

  Technical Analysis Indicators - Pandas TA is an easy to use Python 3 Pandas Extension with 150+ Indicators

  Language:Python5k100564986

• ffffffff0x/Digital-Privacy

  Information Protection & OSINT resources | 一个关于数字隐私搜集、保护、清理集一体的方案,外加开源信息收集(OSINT)对抗

  4.7k1017641

• below/HelloSilicon

  An introduction to ARM64 assembly on Apple Silicon Macs

  Language:Assembly4.2k5316277

• AllenDowney/ThinkDSP

  Think DSP: Digital Signal Processing in Python, by Allen B. Downey.

  Language:Jupyter Notebook3.9k237573.2k

• 0voice/learning_mind_map

  2021年【思维导图】盒子，C/C++，Golang，Linux，云原生，数据库，DPDK，音视频开发，TCP/IP，数据结构，计算机原理等

  2.6k503577

• chipsalliance/verible

  Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

  Language:C++1.3k50932198

• riscv-mcu/e203_hbirdv2

  The Ultra-Low Power RISC-V Core

  Language:Verilog1.2k3519323

• alexforencich/verilog-pcie

  Verilog PCI express components

  Language:Verilog1k5048274

• liangkangnan/tinyriscv

  A very simple and easy to understand RISC-V core.

  Language:C1k178181

• chipsalliance/riscv-dv

  Random instruction generator for RISC-V processor verification

  Language:Python97882346320

• sin-x/FPGA

  数字IC相关资料

  85572263

• pulp-platform/pulp

  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

  Language:SystemVerilog4323352116

• chipsalliance/Surelog

  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

  Language:C++3432691367

• markcheno/go-quote

  Yahoo finance/Google finance/Coinbase/Bittrex/Binance/Tiingo historical quote downloader library and cli written in golang

  Language:Go315182380

• Evian-Zhang/learn-assembly-on-Apple-Silicon-Mac

  在 Apple Silicon Mac 上入门汇编语言

  Language:C2407934

• unknown-marketwizards/tradingview-desktop

  Language:TypeScript239191177

• Yumerain/EA-MQL4

  MQL4编程实现外汇自动化交易

  Language:MQL412513480

• marcoz001/axi-uvm

  yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/

  Language:SystemVerilog955749

• nachumk/systemverilog.vim

  SystemVerilog vim scripts

  Language:Vim Script65111622

• twomonkeyclub/UART

  ARM中通过APB总线连接的UART模块

  Language:Verilog55329

• samgozman/AO-MACD-cross-tradingview

  Oscillator for Tradingview based on MACD and Awesome Oscillator. This oscillator is designed to identify potential price changes as part of a trend movement.

  28316

• muneeb-mbytes/axi4_avip

  Development of AXI4 Accelerated VIP

  Language:SystemVerilog252410

• GZ315200/stock_learning

  来这里学股票知识吧！！！！

  24206

• ArgonDesign/acov

  Generator of functional coverage tracking code for Verilog projects

  Language:Haskell45107