liaojingmath's Stars
WerWolv/ImHex
🔍 A Hex Editor for Reverse Engineers, Programmers and people who value their retinas when working at 3 AM.
USTC-Resource/USTC-Course
:heart:**科学技术大学课程资源
ctgk/PRML
PRML algorithms implemented in Python
kxxwz/SJTU-Courses
上海交通大学课程资料分享
karpathy/arxiv-sanity-preserver
Web interface for browsing, search and filtering recent arxiv submissions
YosysHQ/yosys
Yosys Open SYnthesis Suite
wavedrom/wavedrom
:ocean: Digital timing diagram rendering engine
jikeytang/sublime-text
sublime-text
mit-biomimetics/Cheetah-Software
Nate711/StanfordDoggoProject
Stanford Doggo is an open source quadruped robot that jumps, flips, and trots!
vedderb/bldc
The VESC motor control firmware
XUANTIE-RV/wujian100_open
IC design and development should be faster,simpler and more reliable
YosysHQ/nextpnr
nextpnr portable FPGA place and route tool
vedderb/bldc-hardware
Brushless DC Motor controller from Benjamin Vedder
balzer82/Kalman
Some Python Implementations of the Kalman Filter
wavedrom/wavedrom.github.io
Digital timing diagram editor
WangXuan95/FPGA-FOC
FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器,用于驱动BLDC/PMSM电机。
clorymmk/CodeTransmit
基于python开发的编码转换工具,图形化界面基于pyside2(qt5)开发。 支持批量转换任意格式的文件编码; 可将文件编码转为UTF-8 BOM 、UTF-8、GB2312中的任意一种格式;
ziyinq/Bimocq
Efficient and Conservative Fluids Using Bidirectional Mapping
nandland/spi-master
SPI Master for FPGA - VHDL and Verilog
horychen/ACMSIMC_TUT
AC Machine Simulation in C (Tutorial Version)
unitreerobotics/Publications
Here the publications are all made by Unitree Robotics. https://www.unitree.com
cirosantilli/vcdvcd
Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.
m-labs/tdc-core
A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs
pontazaricardo/Verilog_Calculator_Matrix_Multiplication
This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
RuiMachado39/TDC
Verilog implementation of a tapped delay line TDC
qwhxm/1.5-column-cv
XeTeX CV template with a "1.5-column" layout.
AlxyF/CAN-fpga
https://en.wikipedia.org/wiki/CAN_bus
RayDMR/FieldOrientedControl
FOC in FPGA implementation using MATLAB Simulink VDH code generation
MDNALAM/Development-and-Control-of-converter-for-1.5-MW-PMSG
the main tasks which have been done in this prethesis were a suitable 3 level FC converter design for the machine side and the corresponding losses calculation of the converter. In addition to the previous task the thermal model also realized which shows the temperature status in the IGBTs, diodes, junctions, heat sinks and in the end the efficiency curve is presented to show the overall performance of the designed converter. The efficiency found was approximately 98.5%.