liaojingmath

liaojingmath's Stars

• WerWolv/ImHex

  🔍 A Hex Editor for Reverse Engineers, Programmers and people who value their retinas when working at 3 AM.

  Language:C++44.7k4831.2k1.9k

• USTC-Resource/USTC-Course

  :heart:**科学技术大学课程资源

  Language:C++14.9k568133.5k

• ctgk/PRML

  PRML algorithms implemented in Python

  Language:Jupyter Notebook11.4k417243.3k

• kxxwz/SJTU-Courses

  上海交通大学课程资料分享

  8.5k328132.1k

• karpathy/arxiv-sanity-preserver

  Web interface for browsing, search and filtering recent arxiv submissions

  Language:Python5.1k1681131.3k

• YosysHQ/yosys

  Yosys Open SYnthesis Suite

  Language:C++3.5k1361.7k886

• wavedrom/wavedrom

  :ocean: Digital timing diagram rendering engine

  Language:JavaScript3k90340365

• jikeytang/sublime-text

  sublime-text

  2.8k2197597

• mit-biomimetics/Cheetah-Software

  Language:C++2.6k12795918

• Nate711/StanfordDoggoProject

  Stanford Doggo is an open source quadruped robot that jumps, flips, and trots!

  2.4k18854736

• vedderb/bldc

  The VESC motor control firmware

  Language:C2.2k1913041.4k

• XUANTIE-RV/wujian100_open

  IC design and development should be faster，simpler and more reliable

  Language:Verilog1.9k14046572

• YosysHQ/nextpnr

  nextpnr portable FPGA place and route tool

  Language:C++1.3k72432243

• vedderb/bldc-hardware

  Brushless DC Motor controller from Benjamin Vedder

  Language:KiCad1.1k1760502

• balzer82/Kalman

  Some Python Implementations of the Kalman Filter

  Language:Jupyter Notebook1.1k4622367

• wavedrom/wavedrom.github.io

  Digital timing diagram editor

  Language:JavaScript9356671160

• WangXuan95/FPGA-FOC

  FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

  Language:Verilog5441214167

• clorymmk/CodeTransmit

  基于python开发的编码转换工具，图形化界面基于pyside2（qt5）开发。 支持批量转换任意格式的文件编码； 可将文件编码转为UTF-8 BOM 、UTF-8、GB2312中的任意一种格式；

  Language:Python3803181

• ziyinq/Bimocq

  Efficient and Conservative Fluids Using Bidirectional Mapping

  Language:C++35517669

• nandland/spi-master

  SPI Master for FPGA - VHDL and Verilog

  Language:VHDL25411496

• horychen/ACMSIMC_TUT

  AC Machine Simulation in C (Tutorial Version)

  Language:C223210119

• unitreerobotics/Publications

  Here the publications are all made by Unitree Robotics. https://www.unitree.com

  695027

• cirosantilli/vcdvcd

  Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.

  Language:Python5661522

• m-labs/tdc-core

  A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs

  Language:Verilog5611127

• pontazaricardo/Verilog_Calculator_Matrix_Multiplication

  This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.

  Language:Verilog46218

• RuiMachado39/TDC

  Verilog implementation of a tapped delay line TDC

  Language:Verilog363411

• qwhxm/1.5-column-cv

  XeTeX CV template with a "1.5-column" layout.

  Language:TeX211110

• AlxyF/CAN-fpga

  https://en.wikipedia.org/wiki/CAN_bus

  Language:Verilog12104

• RayDMR/FieldOrientedControl

  FOC in FPGA implementation using MATLAB Simulink VDH code generation

  Language:VHDL12205

• MDNALAM/Development-and-Control-of-converter-for-1.5-MW-PMSG

  the main tasks which have been done in this prethesis were a suitable 3 level FC converter design for the machine side and the corresponding losses calculation of the converter. In addition to the previous task the thermal model also realized which shows the temperature status in the IGBTs, diodes, junctions, heat sinks and in the end the efficiency curve is presented to show the overall performance of the designed converter. The efficiency found was approximately 98.5%.

  Language:MATLAB6101