Here are some of my studies that I carry out using the Verilog language.
If my code has helped you, please consider sponsoring me 💙
Sponsor: melchisedech333
Twitter: Melchisedech333
LinkedIn: Melchisedech Rex
Blog: melchisedech333.github.io
:space_invader: My studies with Verilog and notions of digital systems.
VerilogBSD-3-Clause
Here are some of my studies that I carry out using the Verilog language.
If my code has helped you, please consider sponsoring me 💙
Sponsor: melchisedech333
Twitter: Melchisedech333
LinkedIn: Melchisedech Rex
Blog: melchisedech333.github.io