misadrik

misadrik's Stars

• torvalds/linux

  Linux kernel source tree

  Language:C183k7.8k054.2k

• ohmyzsh/ohmyzsh

  🙃 A delightful community-driven (with 2,400+ contributors) framework for managing your zsh configuration. Includes 300+ optional plugins (rails, git, macOS, hub, docker, homebrew, node, php, python, etc), 140+ themes to spice up your morning, and an auto-update tool that makes it easy to keep up with the latest updates from the community.

  Language:Shell174k2.6k4.8k25.9k

• jlevy/the-art-of-command-line

  Master the command line, in one page

  154k2.8k25314.6k

• home-assistant/core

  :house_with_garden: Open source home automation that puts local control and privacy first.

  Language:Python74k1.3k54.2k31k

• ageitgey/face_recognition

  The world's simplest facial recognition api for Python and the command line

  Language:Python53.5k1.6k1.3k13.5k

• ziishaned/learn-regex

  Learn regex the easy way

  45.7k899866.2k

• ryanhanwu/How-To-Ask-Questions-The-Smart-Way

  本文原文由知名 Hacker Eric S. Raymond 所撰寫，教你如何正確的提出技術問題並獲得你滿意的答案。

  Language:JavaScript31.2k419295.7k

• MatsuriDayo/NekoBoxForAndroid

  NekoBox for Android / sing-box / universal proxy toolchain for Android

  Language:Kotlin11.9k94755997

• MakiNaruto/Automatic_ticket_purchase

  大麦网抢票脚本

  Language:Python4.4k2087844

• chipsalliance/chisel

  Chisel: A Modern Hardware Design Language

  Language:Scala4k1511.1k602

• open-sdr/openwifi

  open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

  Language:C3.9k132345659

• SI-RISCV/e200_opensource

  Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

  Language:Verilog2.6k229431k

• lowRISC/opentitan

  OpenTitan: Open source silicon root of trust

  Language:SystemVerilog2.6k1066.9k781

• darklife/darkriscv

  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

  Language:Verilog2.1k9440286

• analogdevicesinc/hdl

  HDL libraries and projects

  Language:Verilog1.5k159871.5k

• alexforencich/verilog-axi

  Verilog AXI components for FPGA implementation

  Language:Verilog1.5k5371454

• JannsenYang/dingdong-helper

  叮咚自动下单 并发调用接口方式 多人高峰期实战反馈10秒以内成功 自动将购物车能买的商品全部下单 只需自行编辑购物车和最后支付即可

  Language:Java1.3k25235494

• ZipCPU/zipcpu

  A small, light weight, RISC CPU soft core

  Language:Verilog1.3k6228157

• doonny/PipeCNN

  An OpenCL-based FPGA Accelerator for Convolutional Neural Networks

  Language:C1.3k73176370

• alexforencich/verilog-pcie

  Verilog PCI express components

  Language:Verilog1.1k5251304

• pulp-platform/axi

  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

  Language:SystemVerilog1.1k39122268

• KastnerRG/riffa

  The RIFFA development repository

  Language:Verilog7787048315

• pulp-platform/common_cells

  Common SystemVerilog components

  Language:SystemVerilog5191958145

• gxh27954/damai_requests

  大麦网H5、小程序、APP抢票解决

  251103222

• lucky-wfw/ARM_AMBA_Design

  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.

  Language:Verilog1113334

• adki/gen_amba

  AMBA bus generator including AXI, AHB, and APB

  Language:C905439

• sycuricon/starship

  Run rocket-chip on FPGA

  Language:Scala613421

• chiggs/UVM

  Mirror of the Universal Verification Methodology from sourceforge

  Language:SystemVerilog326012

• govindjeevan/Weighted-Round-Robin-Arbiter

  Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components

  Language:Verilog18002

• mammenx/synesthesia_zen

  Next Gen version of Synesthesia

  Language:Verilog3241