RV32E mode - assertions implement with errors

[golikovav]

In RV32E mode, when define SCR1_RVE_EXT, tests can't be completted.

In file "scr1_pipe_csr.sv" signal "instret_nexc" not protected by SCR1_CSR_REDUCED_CNT, in some of assertions

Removing unprotected assertions don't let pass the tests anyway, simulation hangs...

[dp-sc]

Hi,
We will fix the assertion to resolve this issue.
Unfortunately, you couldn't run the tests for RV32E configuration at the moment:

1. There is no support RV32E in RISCV toolchain (riscv-software-src/riscv-tools#59).
2. The RISCV tests use upper 16 registers which are out of the RV32E configuration.