The behavior of Stepping through DCSR.step and DMCONTROL.resumereq

[shipherd]

Hi,

I was wondering why do I have to Halt the hart again after a step and before the next step? I have tested that the hart must be halt (DMCONTROL.haltreq) again after a resume request (DMCONTROL.resumereq), otherwise the next step (resume request) would not work.

To my understanding on "riscv-debug-release.pdf, section 'Appendix B.5'", should not the hart be halt automatically after the resume request?

Thank you. :-)

[achuykov-sc]

Hi @shipherd,

Please excuse for a delayed reply. I've forwarded your question to R&D and will keep you posted.

Best regards,
Alexander

[dk-sc]

Hi @shipherd ,
Sorry for a delayed reply. We got answer from our R&D:

Actually, after resuming a debugger must wait until DMSTATUS.resumeack = 1, and then clear it. Otherwise, if the HART is halted after single step, and DMSTATUS.resumeack = 1 so far, writing of 1 to DMCONTROL.resumereq again virtually does nothing (as DMCONTROL.resumereq already =1 at that moment from the previous resuming).

To clear DMSTATUS.resumeack, a debugger must write DMCONTROL.resumereq = 0. After that next resuming is possible.

In your case, writing of 0x80000001 to DMCONTROL just after resume not only sets haltreq bit (which is useless in that context), but also clears resumereq (and DMSTATUS.resumeack), and that fulfills the requirement above. So, after resuming you should write DMCONTROL = 0x00000001 instead of 0x80000001.

Best regards,
Daria