/Digital_projects_in_Verilog_SystemC

Inference Design, Behavioral simulations, and Hardware Implementation.

Primary LanguageVerilog

Verilog/C/C++_projects-

Inference Design, Simulations, and Hardware Implementation.

This is repository for some of my FPGA projects. All codes are simulated and verified on testbench or on hardware.

Software: Xilinx Vivado 2020.1 and 2018

Hardwares: Development Board with Xilinx Zynq-7000 SoC

Software development on ARM processor was done on Xilinx SDK or Vivado HLS

Some high level codes in C++ were simulated on EDA playground @ https://www.edaplayground.com/

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