HUI1ZHOU

HUI1ZHOU's Stars

• pjreddie/darknet

  Convolutional Neural Networks

  Language:C25.7k9112.4k21.3k

• AlexeyAB/darknet

  YOLOv4 / Scaled-YOLOv4 / YOLO - Neural Networks for Object Detection (Windows and Linux version of Darknet )

  Language:C21.6k4858.3k8k

• oneapi-src/oneDNN

  oneAPI Deep Neural Network Library (oneDNN)

  Language:C++3.6k1861.3k985

• lowRISC/opentitan

  OpenTitan: Open source silicon root of trust

  Language:SystemVerilog2.5k1056.7k745

• alexforencich/verilog-ethernet

  Verilog Ethernet components for FPGA implementation

  Language:Verilog2.2k115161676

• corundum/corundum

  Open source FPGA-based NIC and platform for in-network compute

  Language:Verilog1.6k88163410

• pConst/basic_verilog

  Must-have verilog systemverilog modules

  Language:Verilog1.6k581368

• alexforencich/verilog-axi

  Verilog AXI components for FPGA implementation

  Language:Verilog1.4k5270437

• alexforencich/verilog-pcie

  Verilog PCI express components

  Language:Verilog1.1k5049286

• myhdl/myhdl

  The MyHDL development repository

  Language:Python1k79204247

• KastnerRG/riffa

  The RIFFA development repository

  Language:Verilog7617147311

• alexforencich/verilog-axis

  Verilog AXI stream components for FPGA implementation

  Language:Python7164721222

• Digilent/vivado-library

  Language:C5575959308

• alexforencich/verilog-i2c

  Verilog I2C interface for FPGA implementation

  Language:Verilog515349170

• alexforencich/verilog-uart

  Verilog UART

  Language:Verilog4022310126

• Digilent/vivado-boards

  Language:Tcl3814431211

• embedeep/Free-TPU

  Free TPU for FPGA with compiler supporting Pytorch/Caffe/Darknet/NCNN. An AI processor for using Xilinx FPGA to solve image classification, detection, and segmentation problem.

  Language:Shell23710358

• Xilinx/QNN-MO-PYNQ

  Language:Jupyter Notebook2362364114

• CustomizableComputingLab/CustomizableComputingLab.github.io

  Language:HTML1334030

• aquaxis/IPCORE

  Language:Verilog1197063

• alexforencich/verilog-cam

  Verilog Content Addressable Memory Module

  Language:Verilog10012546

• alexforencich/verilog-dsp

  Verilog digital signal processing components

  Language:Python946134

• alexforencich/xfcp

  Extensible FPGA control platform

  Language:Verilog5210720

• aquaxis/gemac

  Gigabit MAC + UDP/TCP/IP offload Engine

  Language:Verilog304118

• aquaxis/aq_mipi_csi2rx_ultrascaleplus

  Language:Verilog272011

• alexforencich/verilog-ft245

  Verilog FT245 to AXI stream interface

  Language:Python264113

• alexforencich/verilog-mersenne

  Verilog implementation of Mersenne Twister PRNG

  Language:Python255011

• aquaxis/FPGAMAG18

  FPGA Magazine No.18 - RISC-V

  Language:Verilog17206

• Digilent/vivado-hierarchies

  Language:C12702

• aquaxis/FPGAMAG

  FPGAマガジン向け Vivadoプロジェクト

  Language:C74