Fields that shall be implemented as wires are still implemented as flops

[Silicon1602]

Fields with sw=r/hw=w shall be simple wires according to Table 12 from the SystemRDL LRM. The compiled example in 5a00d48 shows that

addrmap hierarchical_regfiles {
    regfile {
        reg{
            field {sw=r; hw=w} f1 [15:0];
        } reg_c;
    } regfile_2 [2];
};

generates the following logic:

always_ff @(posedge clk)
begin
        // we or wel property not set
        regfile_2__reg_c__f1_q[gv_a] <= regfile_2__reg_c__f1_in[gv_a];
end // of regfile_2__reg_c__f1's always_ff

but should be

assign regfile_2__reg_c__f1_q[gv_a] = regfile_2__reg_c__f1_in[gv_a];

Other combinations that should create a (static) wire are also not yet implemented.

See the table from the LRM below as reference: