T3KT4K's Stars
capstone-engine/capstone
Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriCore, Webassembly, XCore and X86.
YosysHQ/yosys
Yosys Open SYnthesis Suite
YosysHQ/picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
openhwgroup/cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
riscv-boom/riscv-boom
SonicBOOM: The Berkeley Out-of-Order Machine
amaranth-lang/amaranth
A modern hardware definition language and toolchain based on Python
chipsalliance/verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
openhwgroup/cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
berkeley-abc/abc
ABC: System for Sequential Logic Synthesis and Formal Verification
m-labs/nmigen
A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
emsec/hal
HAL – The Hardware Analyzer
riscv-non-isa/riscv-arch-test
pulp-platform/pulp-dronet
A deep learning-powered visual navigation engine to enables autonomous navigation of pocket-size quadrotor - running on PULP
openhwgroup/core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
f4pga/f4pga-arch-defs
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
eternagame/superfolder-covid-mrna-vaccines
SuperFolder COVID mRNA vaccines, stabilized for in vitro storage and shipping
ultraembedded/exactstep
Instruction set simulator for RISC-V, MIPS and ARM-v6m
YosysHQ/mcy
Mutation Cover with Yosys (MCY)
GaloisInc/grift
Galois RISC-V ISA Formal Tools