chili-chips-ba/openCologne

Issues

• P&R Error: ERangeError when connecting BUFG to user logic in GateMate FPGA

  #36 opened in 4 hours
  2

• P_R '-om' default is set agressively and does not match Olimex default

  #35 opened 20 hours ago
  1

• Out of context / Virtual Pin Support

  #34 opened 5 days ago
  2

• WANTED: IOSERDES for GateMate

  #33 opened 11 days ago
  0

• Issue with using sv2v for a simple Blinky example

  #32 opened 19 days ago
  1

• No warning issued for unconstrained ports

  #31 opened a month ago
  4

• Mismatch in post-PnR sim and chip operation

  #30 opened a month ago
  1

• Error When Adding synth_gatemate Command in CDC Workflow

  #29 opened 5 days ago
  5

• LUTRAM for CologneChip?!

  #28 opened 2 months ago
  13

• Error 10 on simple keyboard module

  #27 opened 5 days ago
  9

• Validation and introduction of CDC Linter into project QA workflow

  #26 opened 5 days ago
  24

• Undefined behavior in synthesis depending on the bit width of variables

  #25 opened 2 months ago
  16

• GHDL-YOSYS-PLUGIN error: cannot find "std" library

  #24 opened a month ago
  1

• Error in GateMate p_r tool inferring CC_MULT

  #23 opened 2 months ago
  18

• GateMate simulation quirks and problems

  #22 opened 7 days ago
  4

• FATAL ERROR in GateMate p_r Tools for OPL3 FM Synthesizer

  #21 opened 2 months ago
  6

• Issue with inout port of constraint file

  #20 opened 2 months ago
  6

• Issue with ILA using Olimex GateMate board

  #19 opened 2 months ago
  9

• Timing constraints and 'report_timing' in CologneChip proprietary PNR?!

  #18 opened 2 months ago
  10

• Improper UART synthesis

  #17 opened 2 months ago
  15

• OPL3 FM Synthesizer Synthesis and Simulation Issues

  #16 opened 7 days ago
  33

• PCB Feature Request: Simple IO expander for Onlimex Misc connector

  #15 opened 3 months ago
  2

• CC_PLL Verilog simulation model bug

  #14 opened 2 months ago
  4

• GateMate Yosys in the CologneChip tool package is outdated

  #13 opened 7 days ago
  1

• PCB Feature Request: Plug-and-Play compatibility of ULX5M FPGA pinout to Olimex

  #12 opened 3 months ago
  0

• UART Receiver and Transmitter Not Functioning on Olimex GateMate Board

  #11 opened 3 months ago
  2

• GateMate Constraint File Pin Declaration Format

  #10 opened 2 months ago
  7

• PCB Feature Request: Provide 3.5mm Audio Jacks

  #9 opened 3 months ago
  1

• GateMate - Verilator relationship

  #8 opened 5 days ago
  2

• GateMate pre-packaged downloader does not work with Olimex board

  #7 opened 2 months ago
  4

• PCB Feature Request: Provide sufficient number of LEDs and Push-Buttons, via 1-Wire GPIO expander

  #6 opened 3 months ago
  0

• PCB Feature Request: Provide good dual analog OpAmp

  #5 opened 3 months ago
  0

• PCB Feature Request: Provision hooks for per-rail current measurements

  #4 opened 3 months ago
  0

• GateMate SystemVerilog support

  #3 opened 7 days ago
  28

• Error after trying to build Yosys for Linux

  #2 opened 4 months ago
  1

• 1.Blinky 'make_impl' command gives 'FATAL ERROR: Input CLK_REF of net 86 must have dedicated CLK pin connection'

  #1 opened 4 months ago
  1