magicalyu's Stars
openai/whisper
Robust Speech Recognition via Large-Scale Weak Supervision
iamadamdev/bypass-paywalls-chrome
Bypass Paywalls web browser extension for Chrome and Firefox.
imDazui/Tvlist-awesome-m3u-m3u8
直播源相关资源汇总 📺 💯 IPTV、M3U —— 勤洗手、戴口罩,祝愿所有人百毒不侵
YanG-1989/m3u
直播源
tldraw/make-real
Draw a ui and make it real
yuka-friends/Windrecorder
Windrecorder is a memory search app by records everything on your screen in small size, to let you rewind what you have seen, query through OCR text or image description, and get activity statistics.
The-OpenROAD-Project/OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
linuxmint/warpinator
Share files across the LAN
olofk/fusesoc
Package manager and build abstraction tool for FPGA/ASIC development
songquanpeng/go-file
基于 Go 的文件分享工具,仅单可执行文件,开箱即用,内置图床和视频播放页面. File sharing tool based on Go.
spxak1/weywot
My notes on using Linux
moseoridev/WarpShare
An Open-source AirDrop Alternative
wileyyugioh/zotmoov
Zotero plugin to automatically move attachments and link them
Xilinx/RapidWright
Build Customized FPGA Implementations for Vivado
lwfinger/rtl8852au
sylefeb/a5k
Another World on a chip
gatecat/nextpnr-xilinx
Experimental flows using nextpnr for Xilinx devices
vinint/MoKee-WarpShare
移植魔趣的“跃传”,支持Android向Mac传输数据
byuccl/spydrnet
A flexible framework for analyzing and transforming FPGA netlists. Official repository.
tokuhirom/Perl-Build
djn3m0/debit
Reverse-engineering tools for FPGA bitstreams, Altera and Xilinx
FPGA-Research-Manchester/byteman
Bitstream relocation and manipulation tool.
brouhaha/xchange
Change part number or package in a Xilinx 7-series FPGA bitstream
secworks/sha512
Verilog implementation of the SHA-512 hash function.
UNSAMDCI/PDK_ONC5
Educational Design Kit for Synopsys Tools with a set of Characterized Standard Cell Library
silverback97/universal_mx_keys_remap
Re-Mapping Universal Logitech Mx Keys Keyboard on MacOS
epfl-vlsc/bitfiltrator
Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats
secworks/uart
A Universal asynchronous receiver/transmitter (UART) implemented in Verilog.
FPGA-Research-Manchester/nextpnr-fabulous
JensRestemeier/EdifTests
A few experiments using the SpyDrNet netlist library.