Load in shadow of `mul`/`div` doesn't write loaded data back to GPRs.

[ben-marshall]

If a load is immediately before a mul* or div* instruction, then it does not progress into the write-back stage fast enough to "catch" returning read data. The writeback stage then ignores the returned load data and no GPR write occurs.

• There is no unit test to catch this.
• The riscv-formal framework doesn't catch it because the proofs aren't allowed to run for long enough.

Fixes:

• Allow memory stage instructions to progress before EX stage instructions are finished.
• Add unit test to catch regressions on this.