scarv/scarv-cpu

Core Complex

ben-marshall opened this issue · 1 comments

Implement a "core complex" module, which wraps the CPU core with:

  • A dual port, tightly coupled RAM.
  • A single port, tightly coupled ROM.
  • The TRNG / pollentropy entropy source.
  • The memory mapped machine timers and counters. See#28.
  • The physical memory protection registers, when implemented. See#37.
  • An "external" memory port out of the CCX to peripherals in a wider SoC system.

The core-complex wraps the CPU in a "drop-in" style module, containing everything the CPU needs to run. This simplifies the construction of the SoC significantly, and lets people re-use it more easily.

Todo List:

  • RAM / ROM modules.
  • scarv_ccx_top module.
  • Interconnect
    • Arbiter
    • Router
    • Hooks for PMP checks. - Decided PMP will live inside the core level.
    • Memory interface definition.
  • Memory mapped IO module for:
    • TRNG access.
    • Memory mapped counters.

Closed with 456866f.