seldridge

seldridge's Stars

• Experience-Monks/math-as-code

  a cheat-sheet for mathematical notation in code form

  15.3k408481.1k

• halide/Halide

  a language for fast, portable data-parallel computation

  Language:C++6k2362.7k1.1k

• TigerVNC/tigervnc

  High performance, multi-platform VNC client and server

  Language:C++5.5k1501.4k987

• airsonic/airsonic

  :satellite: :cloud: :notes:Airsonic, a Free and Open Source community driven media server (fork of Subsonic and Libresonic)

  Language:Java2k681.3k240

• itsfrank/MinecraftHDL

  A Verilog synthesis flow for Minecraft redstone circuits

  Language:SystemVerilog1.2k181126

• verilog-to-routing/vtr-verilog-to-routing

  Verilog to Routing -- Open Source CAD Flow for FPGA Research

  Language:C++1.1k681k403

• KLayout/klayout

  KLayout Main Sources

  Language:C++847451.2k213

• VUnit/vunit

  VUnit is a unit testing framework for VHDL/SystemVerilog

  Language:VHDL76051628271

• PrincetonUniversity/openpiton

  The OpenPiton Platform

  Language:Assembly6685771217

• black-parrot/black-parrot

  A Linux-capable RISC-V multicore for and by the world

  Language:SystemVerilog65825412184

• vmware-archive/cascade

  A Just-In-Time Compiler for Verilog from VMware Research

  Language:C++4383012944

• riscvarchive/riscv-qemu

  QEMU with RISC-V (RV64G, RV32G) Emulation Support

  Language:C3897997155

• cornell-brg/pymtl

  Python-based hardware modeling framework

  Language:Python2384415782

• ucb-bar/chiseltest

  The batteries-included testing and formal verification library for Chisel-based RTL designs.

  Language:Scala2312319476

• ZipCPU/dblclockfft

  A configurable C++ generator of pipelined Verilog FFT cores

  Language:C++230141335

• soDLA-publishment/soDLA

  Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated

  Language:Verilog227212049

• cornell-brg/pydgin

  A (Py)thon (D)SL for (G)enerating (In)struction set simulators.

  Language:Python166372229

• ucb-bar/hwacha

  Microarchitecture implementation of the decoupled vector-fetch accelerator

  Language:Scala149201942

• uclid-org/uclid

  UCLID5: formal modeling, verification, and synthesis of computational systems

  Language:Scala138146232

• google/bottlerocket

  Language:Scala10917024

• ucb-bar/midas

  FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL

  Language:Scala99332015

• beetbox/aura

  music library REST API

  Language:JavaScript7625249

• GaloisInc/grift

  Galois RISC-V ISA Formal Tools

  Language:Haskell562038

• freechipsproject/firrtl-interpreter

  A scala based simulator for circuits described by a LoFirrtl file

  Language:Scala47264523

• aswaterman/trainwreck

  Original RISC-V 1.0 implementation. Not supported.

  Language:Verilog415214

• jerry-D/SYMPL-GP-GPU-Compute-Engines

  Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in open-source Verilog RTL for 32-bit single-precision floating-point accelerated applications.

  2211114

• IBM/microprobe

  Microprobe: Microbenchmark generation framework

  Language:Python21111817

• ymanerka/pipeproof

  PipeProof

  Language:Coq11211

• beetbox/amaranth

  command-line AURA client

  Language:Rust5700

• jkopanski/firrtl

  Haskell FIRRTL implementation

  Language:Haskell3351