make build # build the design
make sim # runs the testbench
make view # opens the waveform in gtkwave
make lint # lint with Verilator
make usage # report generic cell utilization
make clean # remove build filessifferman/verilog_template
A template for starting a Verilog project with FuseSoC integration, Icarus simulation, Verilator linting, Yosys usage report, and VS Code syntax highlighting.
Makefile