Which files are need to be synthesized?

[yunchenlo]

Dear Sir,

I am trying to synthesize scr1 using dc_shell.
As all files are written in system verilog, I am wondering which files need to be synthesized?

Currently I put all files list in src/axi_top.files and src/core.files to analyze command in dc_shell

Thank you,
Yun-Chen Lo

[ar-sc]

hi Yun-Chen, yes, these are correct lists.

If you are doing synthesis, please pay attention to library-specific cells, which need to be set properly in the instance. Depending on the configuration you use, you may need to modify these:
scr1\src\core\primitives\scr1_cg.sv - for library specific clock gating element
scr1\src\top\scr1_dp_memory.sv - for library specific memory modules
Will add section on that in the user guide in the coming release.

cheers, a

[eb-sc]

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