Verilator timing required?

Hello,

Just wanted to point out that the quickstart with Verilator is not working.

Cloning the repository and doing:

make run_verilator CFG=MAX BUS=AHB TRACE=0 TARGETS="hello"

Gives out a error that delayed assignments are used.
Particularly one block of code is an issue:

scr1/src/tb/scr1_top_tb_ahb.sv

Lines 261 to 272 in d8ba8e5

    
           `ifdef SCR1_DBG_EN 
        
           initial begin 
        
               trst_n  = 1'b0; 
        
               tck     = 1'b0; 
        
               tdi     = 1'b0; 
        
               #900ns trst_n   = 1'b1; 
        
               #500ns tms      = 1'b1; 
        
               #800ns tms      = 1'b0; 
        
               #500ns trst_n   = 1'b0; 
        
               #100ns tms      = 1'b1; 
        
           end 
        
           `endif // SCR1_DBG_EN

Similar for AXI testbench.
I didn't analyze what was the intended function behind it, but you either forgot `ifndef VERILATOR around it or to disable the SCR1_DBG_EN for verilator simulation.

Other option is to bump the Verilator version to > 5.0 and use the --timing feature.
For this you need also C++ compiler with C++20 (coroutines) support, but I tested it and it works.

Hi @Risto97,

Thank you for reporting. The issue appears in 5.x version of the Verilator. So, if you are not able to use C++20 compiler, you could use older versions like 4.102. If you have a possibility to use C++20, you could add --timing option for 5.x version of the Verilator.

We will update Makefiles during next maintenance.

Best regards,
Alexander

	`ifdef SCR1_DBG_EN
	initial begin
	trst_n = 1'b0;
	tck = 1'b0;
	tdi = 1'b0;
	#900ns trst_n = 1'b1;
	#500ns tms = 1'b1;
	#800ns tms = 1'b0;
	#500ns trst_n = 1'b0;
	#100ns tms = 1'b1;
	end
	`endif // SCR1_DBG_EN