wxz1003083273's Stars
pgmpy/pgmpy
Python Library for learning (Structure and Parameter), inference (Probabilistic and Causal), and simulations in Bayesian Networks.
Helpsoftware/fanqiang
SS & SSR & V2ray & Clash & Surge 等免费节点及订阅地址分享和推荐,各种实用网站和软件分享。 此页面仅作学习交流用,请用于查找资料,不要做任何违法行为。所有资源均来自互联网,非盈利目的,仅供大家交流学习使用,出现一切问题概不负责。
analogdevicesinc/hdl
HDL libraries and projects
alexforencich/verilog-axi
Verilog AXI components for FPGA implementation
ultraembedded/cores
Various HDL (Verilog) IP Cores
PyHDI/Pyverilog
Python-based Hardware Design Processing Toolkit for Verilog HDL
zachjs/sv2v
SystemVerilog to Verilog conversion
pulp-platform/common_cells
Common SystemVerilog components
ZipCPU/wb2axip
Bus bridges and other odds and ends
pulp-platform/pulp
This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
rmcantin/bayesopt
BayesOpt: A toolbox for bayesian optimization, experimental design and stochastic bandits.
lowRISC/style-guides
lowRISC Style Guides
RTimothyEdwards/open_pdks
PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open processes.
chipsalliance/VeeRwolf
FuseSoC-based SoC for VeeR EH1 and EL2
chipsalliance/Cores-VeeR-EL2
VeeR EL2 Core
ucb-bar/chiseltest
The batteries-included testing and formal verification library for Chisel-based RTL designs.
efabless/caravel_mpw-one
Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
ben-marshall/verilog-parser
A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.
pulp-platform/pulp-sdk
ben-marshall/uart
A simple implementation of a UART modem in Verilog.
dadongshangu/async_FIFO
This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is coded by me(Xianghzi Meng)
Practical-UVM-Step-By-Step/Practical-UVM-IEEE-Edition
This is the repository for the IEEE version of the book
wangeddie67/ESYSim
www-asics-ws/usb1_device
USB 1.1 Device IP Core
ben-marshall/verilog-doc
A basic documentation generator for Verilog, similar to Doxygen.
ben-marshall/microcoder
Define custom assembly-like instructions and use them to write programs which are transpiled into synthesisable Verilog code.
ben-marshall/verilog-probe
A very small and simple debug probe designed to be very easy to interface with and be usable via SPI, JTAG and UART.
freesgl/fanqiang-software-free-download
免费翻墙软件收集和下载
Crimsonninja/elen613
Code for ELEN613: SOC Verification
dpc525/riscv-dv
SV/UVM based instruction generator for RISC-V processor verification