D3boker1

D3boker1's Stars

• TomSchimansky/CustomTkinter

  A modern and customizable python UI-library based on Tkinter

  Language:Python11.5k1111.4k1.1k

• seemoo-lab/openhaystack

  Build your own 'AirTags' 🏷 today! Framework for tracking personal Bluetooth devices via Apple's massive Find My network.

  Language:Swift8.5k132185466

• ahmedbahaaeldin/From-0-to-Research-Scientist-resources-guide

  Detailed and tailored guide for undergraduate students or anybody want to dig deep into the field of AI with solid foundation.

  7.5k210141k

• OpenXiangShan/XiangShan

  Open-source high-performance RISC-V processor

  Language:Scala4.8k87400654

• wavedrom/wavedrom

  :ocean: Digital timing diagram rendering engine

  Language:JavaScript3k90340365

• riscv-software-src/riscv-isa-sim

  Spike, a RISC-V ISA Simulator

  Language:C2.4k130849856

• epasveer/seer

  Seer - a gui frontend to gdb

  Language:C++2.1k1717769

• Wenzel/awesome-virtualization

  Collection of resources about Virtualization

  1.7k899288

• lowRISC/ibex

  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

  Language:SystemVerilog1.4k97834541

• chipsalliance/verible

  Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

  Language:C++1.4k48956206

• facebookexperimental/hermit

  Hermit launches linux x86_64 programs in a special, hermetically isolated sandbox to control their execution. Hermit translates normal, nondeterministic behavior, into deterministic, repeatable behavior. This can be used for various applications, including replay-debugging, reproducible artifacts, chaos mode concurrency testing and bug analysis.

  Language:Rust1.2k132931

• alexforencich/verilog-pcie

  Verilog PCI express components

  Language:Verilog1.1k5051299

• pulp-platform/axi

  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

  Language:SystemVerilog1.1k39120262

• chipsalliance/riscv-dv

  Random instruction generator for RISC-V processor verification

  Language:Python1k82347328

• tandasat/Hypervisor-101-in-Rust

  The materials of "Hypervisor 101 in Rust", a one-day long course, to quickly learn hardware-assisted virtualization technology and its application for high-performance fuzzing on Intel/AMD processors.

  Language:Rust98514966

• PrincetonUniversity/openpiton

  The OpenPiton Platform

  Language:Assembly6375769215

• f4pga/f4pga-arch-defs

  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

  Language:Jupyter Notebook27225630113

• migueltc13/TryHackMe

  Master cybersecurity skills with this TryHackMe free path, includes a collection of my write-ups, solutions and progress tracking.

  Language:Shell23372131

• pulp-platform/cheshire

  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

  Language:Verilog194152046

• dpretet/axi-crossbar

  An AXI4 crossbar implementation in SystemVerilog

  Language:SystemVerilog12031625

• raysalemi/Python4RTLVerification

  Language:Jupyter Notebook12015528

• pulp-platform/carfield

  A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.

  Language:Tcl72133713

• AlSaqr-platform/he-soc

  Language:C30317

• zero-day-labs/riscv-aia

  AIA IP compliant with the RISC-V AIA spec

  Language:SystemVerilog28377

• pulp-platform/culsans

  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol

  Language:C275010

• avpatel/linux

  Linux kernel source tree

  Language:C16904

• bao-project/bao-helloworld

  Language:C10303

• minho-pulp/aia

  8111

• zero-day-labs/riscv-iopmp

  IOPMP IP

  Language:SystemVerilog8001

• pulp-platform/axi-io-pmp

  Input / Output Physical Memory Protection Unit for RISC-V

  Language:SystemVerilog7512