Pinned Repositories
rocket-chip
Rocket Chip Generator
verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
usb3_pipe
USB3 PIPE interface for Xilinx 7-Series
chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
rocket-chip
Rocket Chip Generator
scripts
RTL related scripts to ASIC/FPGA
berkeley-hardfloat
chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
chiseltest
The batteries-included testing and formal verification library for Chisel-based RTL designs.
vtr-verilog-to-routing
Verilog to Routing -- Open Source CAD Flow for FPGA Research
michael-etzkorn's Repositories
michael-etzkorn/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
michael-etzkorn/rocket-chip
Rocket Chip Generator
michael-etzkorn/scripts
RTL related scripts to ASIC/FPGA