CodeMadUser's Stars
adam-maj/tiny-gpu
A minimal GPU design in Verilog to learn how GPUs work from the ground up
chipsalliance/rocket-chip
Rocket Chip Generator
lowRISC/opentitan
OpenTitan: Open source silicon root of trust
openhwgroup/cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
darklife/darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
pConst/basic_verilog
Must-have verilog systemverilog modules
alexforencich/verilog-axi
Verilog AXI components for FPGA implementation
ZipCPU/zipcpu
A small, light weight, RISC CPU soft core
aolofsson/oh
Verilog library for ASIC and FPGA designers
alexforencich/verilog-pcie
Verilog PCI express components
sin-x/FPGA
数字IC相关资料
ultraembedded/cores
Various HDL (Verilog) IP Cores
osresearch/spispy
An open source SPI flash emulator and monitor
stffrdhrn/sdram-controller
Verilog SDRAM memory controller
damdoy/ice40_ultraplus_examples
Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation
suisuisi/FPGA_Library
Vivado诸多IP,包括图像处理等
WangXuan95/FPGA-FixedPoint
Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库,提供算术运算、与浮点数的互相转换,包含单周期和流水线两种实现。
WangXuan95/FPGA-SDcard-Reader-SPI
An FPGA-based SD-card reader via SPI bus, which can read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器(通过SPI总线),可以从FAT16或FAT32格式的SD卡中读取文件。
ultraembedded/core_soc
Basic Peripheral SoC (SPI, GPIO, Timer, UART)
jerry-D/HedgeHog-Fused-Spiking-Neural-Network-Emulator-Compute-Engine
HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx Kintex Ultra Plus brand FPGAs and embedded RISC-V as trainer.
janschiefer/verilog_spi
A simple Verilog SPI master / slave implementation featuring all 4 modes.
suisuisi/FPGAandStudy
帮助大家进行FPGA的入门,分享FPGA相关的优秀文章,优秀项目
zhajio1988/ExtremeDV_UVM
UVM resource from github, run simulation use YASAsim flow
cvonk/FPGA_SPI
Connecting FPGA and Arduino using SPI.
red435/verilog_APB_SPI_interface
SPI interface connect to APB BUS with Verilog HDL
TheMozg/spi-amba-simulation
ITMO SystemC & Verilog assignments - AMBA AHB and SPI
OpenCAPI/omi_device_ice
An example OMI Device FPGA with 2 DDR4 memory ports
charkster/spi_slave_verilog
SPI bus slave and flip-flop register memory map implemented in Verilog 2001 for FPGAs
suisuisi/teroshdl
teroshdl例程
CodeMadUser/cores
Various HDL (Verilog) IP Cores