YiminGao0113

YiminGao0113's Stars

• mindspore-ai/mindspore

  MindSpore is a new open source deep learning training/inference framework that could be used for mobile, edge and cloud scenarios.

  Language:C++4.4k148278714

• SpinalHDL/VexRiscv

  A FPGA friendly 32 bit RISC-V CPU implementation

  Language:Assembly2.5k102337422

• openhwgroup/cva6

  The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

  Language:Assembly2.3k931.1k706

• SpinalHDL/SpinalHDL

  Scala based HDL

  Language:Scala1.7k81755336

• olofk/serv

  SERV - The SErial RISC-V CPU

  Language:Verilog1.5k3863193

• m-labs/migen

  A Python toolbox for building complex digital hardware

  Language:Python1.2k65132211

• riscv-software-src/riscv-tests

  Language:C91978240471

• chipsalliance/Cores-VeeR-EH1

  VeeR EH1 core

  Language:SystemVerilog83358100222

• black-parrot/black-parrot

  A Linux-capable RISC-V multicore for and by the world

  Language:SystemVerilog64224412183

• minerva-cpu/minerva

  A 32-bit RISC-V soft processor

  Language:Python30722632

• Bali10050/FirefoxCSS

  Custom firefox interface

  Language:CSS30252025

• geohot/twitchcore

  It's a core. Made on Twitch.

  Language:Verilog25215227

• IObundle/iob-cache

  Verilog Configurable Cache

  Language:Verilog16782633

• nils-wisiol/pypuf

  Cryptanalysis of Physically Unclonable Functions

  Language:Python80107025

• gplhegde/convolution-flavors

  Implementation of convolution layer in different flavors

  Language:C684126

• antmicro/litex-vexriscv-tensorflow-lite-demo

  TF Lite demo on LiteX/VexRiscv soft RISC-V SoC on a Digilent Arty board

  Language:RobotFramework63192822

• sergachev/spi_mem_programmer

  Small (Q)SPI flash memory programmer in Verilog

  Language:Verilog5511214

• janschiefer/verilog_spi

  A simple Verilog SPI master / slave implementation featuring all 4 modes.

  Language:Verilog45109

• cdeotte/MNIST-CNN-99.5

  Language:C411011

• omega-rg/Cache-Controller

  Two Level Cache Controller implementation in Verilog HDL

  Language:Verilog39108

• DaveBerkeley/serv_soc

  SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.

  Language:Verilog29427

• martinriis/RISC-V-Vector-Processor

  256-bit vector processor based on the RISC-V vector (V) extension

  Language:SystemVerilog28503

• hplp/PiMulator

  Processing in Memory Emulation

  Language:Tcl185105

• opalkelly-opensource/design-resources

  A collection of Opal Kelly provided design resources

  Language:Verilog15339

• ronak66/Direct-Mapped-Cache

  Implementation of Direct-Mapped-Cache to hold 256 blocks, 16 32-bit instruction/Data per block with 32-bit address line

  Language:Verilog14215

• VLSIDA/puffery

  Tools for PUF analysis

  Language:Python10604

• 0xArt/Super_SPI_Master_Verilog

  SPI Master Verilog module

  Language:SystemVerilog8204

• scanakci/linux-on-litex-blackparrot

  Linux on Litex for BlackParrot Core

  Language:Makefile87104

• Bageldoodle/SPI

  Verilog 2001 implementation of part of Microchip's 23A640 SPI Bus low-power serial SRAM.

  Language:Verilog2

• black-parrot-hdk/litex

  Build your hardware, easily!

  Language:C1101