VLSI Flow broken for OpenRoad+Sky130 on chipyard 1.11.0 or above?
Jerry-Tianchen opened this issue · 0 comments
Jerry-Tianchen commented
Background Work
- Yes, I searched the mailing list
- Yes, I searched prior issues
- Yes, I searched the documentation
Chipyard Version and Hash
1.11.0
OS Setup
RedHat 9
Other Setup
Ex: Prior steps taken / Documentation Followed / etc...
Current Behavior
Following exactly the tutorial on Sky130+OpenRoad with 1.11.0's TinyRocketConfig.
Multiple places have been broken in the sky130-OpenRoad flow.
- Clock in Yml doesn't match the actual clock name in the project
- Macro name and number don't match the actual name of Macro in the project, also the number of Macro in DCache seems completely wrong. Yml file says 4 Macros for DCahce and 2 for ICacahe, but after Chisel to RTL, seems only 3 SRAMs are needed in total?
- Syn tool complains cells like "DFF_PP0", which seems to be an async reset FF that Sky130 doesn't support.
Expected Behavior
N/A
Other Information
No response