How to configure asynchronous reset
Opened this issue · 5 comments
Background Work
- Yes, I searched the mailing list
- Yes, I searched the documentation
Feature Description
Hello, I have encountered some questions and would like to seek advice. At present, the RTL I generate under chipyard is synchronously reset. I hope to generate an asynchronous reset system. Are there any configuration options that can be modified？
Motivating Example
Hello, I have encountered some questions and would like to seek advice. At present, the RTL I generate under chipyard is synchronously reset. I hope to generate an asynchronous reset system. Are there any configuration options that can be modified？
The reset pin into the ChipTop is asynchronous w.r.t. any other clock inputs. A reset synchronizer sync's that reset to the clock for the digital logic.
Thank you for your reply, but if I wish to remove the synchronization tool for chiptop. Because I hope to ultimately obtain a digital top system with asynchronous reset.
I added the option "with RequireAsyncReset" in the digital configuration, but there were a series of errors, such as "reset network reset simultaneously connected to async and sync". Do you have any suggestions to solve this problem？
This isn't well supported anymore. To support the complexity of the clocking and reset network for a multi-clock-domain SoC, it was necessary to move to global synchronous reset. Reverting that would be a very invasive change.
Could you describe why you need asynchronous reset for all the digital logic?
Because our project requires this project as a sub IP, but we only use the Digital level
However, other IPs are asynchronous resets, and we hope to achieve global asynchronous resets, including Digital top
Also, may I ask if I can generate a system with Digital as the top-level separately