coremark/dhrystone testing can't get 4.9 CM/MHz with rtl simulation or in FPGA

Question

coremark/dhrystone testing can't get 4.9 CM/MHz with rtl simulation or in FPGA

chithize opened this issue a year ago · 0 comments

HI ,

I tried test cmark, dhrystone testing with latest VeeR EH1, for ICCM, high_perf target, no way can get 4.9 claimed by WD before.
any special compiler or rtl source config needed?