Which signal should I choose to trace Load/Store/pipeline state
ymlei opened this issue · 1 comments
ymlei commented
Hi! I want to trace memory accesses and their target address during the program running on SweRV Core. Which signal should I trace? How about coming to the pipeline state(stall, bypass...)?
deepakpan commented
Which signals specifically you are looking it? Do you want to look at the DCCM access signals in the waves or through the trace port. Please provide more details and I will try to provide the answer.