Formal Verification of SweRV EH1 using riscv-formal

[ShashankVM]

Hello, I am interested in performing formal verification of the SweRV EH1 core using riscv-formal (https://github.com/SymbioticEDA/riscv-formal).

RISC-V formal has been applied for formal verification of picorv32 core that implements RV32IMC Instruction set. Since the SweRV EH1 implements RV32IMC, it would be a good idea to formally verify it using RISC-V Formal. I am working on this project.

Thanks,
Shashank V M