synthesis tool error when IO_DMA_EN => true
Closed this issue · 7 comments
i have my own top-level .vhd file, which internally instantiates neorv32_top.vhd.... wanting to try the latest DMA peripheral, i added IO_DMA_EN => true in the appropriate place....
when i synthesize my design for my iCEBreaker FPGA, however, i receive the following message:
ERROR: cell type 'neorv32_dma' is unsupported (instantiated as 'neorv32_inst.neorv32_dma_complex_true.neorv32_dma_inst')
from what i can tell, the dma IS instantiated in neorv32_top.vhd based on IO_DMA_EN being set....
help -- as this sort of problem is (currently) way above my job-level 😉
What synthesis tool you using? Lattice Radiant or an open-source setup?
Did you add the new neorv32_dma.vhd file to your setup? And did also add this file to the neorv32 library?
i'm using same yosys/ghdl build flow as supported within the neorv32-setups/osflow folder....
my setup uses the neorv32/rtl/core/neorv32_top.vhd file, which itself has been updated in the latest commits to this repo....
as a further experiment, i first set IO_DMA_EN => in one of the neorv32/rtl/processor_template files and then tried building one of the configurations in neorv32-setups/osflow.... same problem....
Oh, I think I have not updated the file list yet (-> https://github.com/stnolting/neorv32-setups/blob/main/osflow/filesets.mk) 🙈 I'll fix that ASAP!
that explains it.... i can certainly make a quick change on my end, so i can proceed....
interesting, but i did NOT have a problem when using vivado to synthesize for the arty FPGA.... why??? because the create_project.tcl script "globs" all the neorv32/rtl/*.vhd files....
neorv32-setup should be up-to-date now.
interesting, but i did NOT have a problem when using vivado to synthesize for the arty FPGA.... why??? because the create_project.tcl script "globs" all the neorv32/rtl/*.vhd files....
Yeah, that might be the reason. 😉
Does your setup work now?
I think this can be closed, right?
yes